SIMD INSTRUCTION SET SUMMARY

Intel® 64 and IA-32 Architectures Software Developer’s Manual

 

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INSTRUCTION SET SUMMARY

5.1.1 Data Transfer Instructions

MOV Move data between general-purpose registers; move data between memory and generalpurpose
or segment registers; move immediates to general-purpose registers
CMOVE/CMOVZ Conditional move if equal/Conditional move if zero
CMOVNE/CMOVNZ Conditional move if not equal/Conditional move if not zero
CMOVA/CMOVNBE Conditional move if above/Conditional move if not below or equal
CMOVAE/CMOVNB Conditional move if above or equal/Conditional move if not below
CMOVB/CMOVNAE Conditional move if below/Conditional move if not above or equal
CMOVBE/CMOVNA Conditional move if below or equal/Conditional move if not above
CMOVG/CMOVNLE Conditional move if greater/Conditional move if not less or equal
CMOVGE/CMOVNL Conditional move if greater or equal/Conditional move if not less
CMOVL/CMOVNGE Conditional move if less/Conditional move if not greater or equal
CMOVLE/CMOVNG Conditional move if less or equal/Conditional move if not greater
CMOVC Conditional move if carry
CMOVNC Conditional move if not carry
CMOVO Conditional move if overflow
CMOVNO Conditional move if not overflow
CMOVS Conditional move if sign (negative)
CMOVNS Conditional move if not sign (non-negative)
CMOVP/CMOVPE Conditional move if parity/Conditional move if parity even
CMOVNP/CMOVPO Conditional move if not parity/Conditional move if parity odd
XCHG Exchange
BSWAP Byte swap
XADD Exchange and add
CMPXCHG Compare and exchange
CMPXCHG8B Compare and exchange 8 bytes
PUSH Push onto stack
POP Pop off of stack
PUSHA/PUSHAD Push general-purpose registers onto stack
POPA/POPAD Pop general-purpose registers from stack
CWD/CDQ Convert word to doubleword/Convert doubleword to quadword
CBW/CWDE Convert byte to word/Convert word to doubleword in EAX register
MOVSX Move and sign extend
MOVZX Move and zero extend

5.1.2 Binary Arithmetic Instructions

ADD Integer add
ADC Add with carry
SUB Subtract
SBB Subtract with borrow
IMUL Signed multiply
MUL Unsigned multiply
IDIV Signed divide
DIV Unsigned divide
INC Increment
DEC Decrement
NEG Negate
CMP Compare

5.1.3 Decimal Arithmetic Instructions

DAA Decimal adjust after addition
DAS Decimal adjust after subtraction
AAA ASCII adjust after addition
AAS ASCII adjust after subtraction
AAM ASCII adjust after multiplication
AAD ASCII adjust before division

5.1.4 Logical Instructions

AND Perform bitwise logical AND
OR Perform bitwise logical OR
XOR Perform bitwise logical exclusive OR
NOT Perform bitwise logical NOT

5.1.5 Shift and Rotate Instructions

SAR Shift arithmetic right
SHR Shift logical right
SAL/SHL Shift arithmetic left/Shift logical left
SHRD Shift right double
SHLD Shift left double
ROR Rotate right
ROL Rotate left
RCR Rotate through carry right
RCL Rotate through carry left

5.1.6 Bit and Byte Instructions

BT Bit test
BTS Bit test and set
BTR Bit test and reset
BTC Bit test and complement
BSF Bit scan forward
BSR Bit scan reverse
SETE/SETZ Set byte if equal/Set byte if zero
SETNE/SETNZ Set byte if not equal/Set byte if not zero
SETA/SETNBE Set byte if above/Set byte if not below or equal
SETAE/SETNB/SETNC Set byte if above or equal/Set byte if not below/Set byte if not carry
SETB/SETNAE/SETCSet byte if below/Set byte if not above or equal/Set byte if carry
SETBE/SETNA Set byte if below or equal/Set byte if not above
SETG/SETNLE Set byte if greater/Set byte if not less or equal
SETGE/SETNL Set byte if greater or equal/Set byte if not less
SETL/SETNGE Set byte if less/Set byte if not greater or equal
SETLE/SETNG Set byte if less or equal/Set byte if not greater
SETS Set byte if sign (negative)
SETNS Set byte if not sign (non-negative)
SETO Set byte if overflow
SETNO Set byte if not overflow
SETPE/SETP Set byte if parity even/Set byte if parity
SETPO/SETNP Set byte if parity odd/Set byte if not parity
TEST Logical compare

5.1.7 Control Transfer Instructions

JMP Jump
JE/JZ Jump if equal/Jump if zero
JNE/JNZ Jump if not equal/Jump if not zero
JA/JNBE Jump if above/Jump if not below or equal
JAE/JNB Jump if above or equal/Jump if not below
JB/JNAE Jump if below/Jump if not above or equal
JBE/JNA Jump if below or equal/Jump if not above
JG/JNLE Jump if greater/Jump if not less or equal
JGE/JNL Jump if greater or equal/Jump if not less
JL/JNGE Jump if less/Jump if not greater or equal
JLE/JNG Jump if less or equal/Jump if not greater
JC Jump if carry
JNC Jump if not carry
JO Jump if overflow
JNO Jump if not overflow
JS Jump if sign (negative)
JNS Jump if not sign (non-negative)
JPO/JNP Jump if parity odd/Jump if not parity
JPE/JP Jump if parity even/Jump if parity
JCXZ/JECXZ Jump register CX zero/Jump register ECX zero
LOOP Loop with ECX counter
LOOPZ/LOOPE Loop with ECX and zero/Loop with ECX and equal
LOOPNZ/LOOPNE Loop with ECX and not zero/Loop with ECX and not equal
CALL Call procedure
RET Return
IRET Return from interrupt
INT Software interrupt
INTO Interrupt on overflow
BOUND Detect value out of range
ENTER High-level procedure entry
LEAVE High-level procedure exit

5.1.8 String Instructions

MOVS/MOVSB Move string/Move byte string
MOVS/MOVSW Move string/Move word string
MOVS/MOVSD Move string/Move doubleword string
CMPS/CMPSB Compare string/Compare byte string
CMPS/CMPSW Compare string/Compare word string
CMPS/CMPSD Compare string/Compare doubleword string
SCAS/SCASB Scan string/Scan byte string
SCAS/SCASW Scan string/Scan word string
SCAS/SCASD Scan string/Scan doubleword string
LODS/LODSB Load string/Load byte string
LODS/LODSW Load string/Load word string
LODS/LODSD Load string/Load doubleword string
STOS/STOSB Store string/Store byte string
STOS/STOSW Store string/Store word string
STOS/STOSD Store string/Store doubleword string
REP Repeat while ECX not zero
REPE/REPZ Repeat while equal/Repeat while zero
REPNE/REPNZ Repeat while not equal/Repeat while not zero

5.1.9 I/O Instructions

IN Read from a port
OUT Write to a port
INS/INSB Input string from port/Input byte string from port
INS/INSW Input string from port/Input word string from port
INS/INSD Input string from port/Input doubleword string from port
OUTS/OUTSB Output string to port/Output byte string to port
OUTS/OUTSW Output string to port/Output word string to port
OUTS/OUTSD Output string to port/Output doubleword string to port

5.1.10 Enter and Leave Instructions

ENTER High-level procedure entry
LEAVE High-level procedure exit

5.1.11 Flag Control (EFLAG) Instructions

STC Set carry flag
CLC Clear the carry flag
CMC Complement the carry flag
CLD Clear the direction flag
STD Set direction flag
LAHF Load flags into AH register
SAHF Store AH register into flags
PUSHF/PUSHFD Push EFLAGS onto stack
POPF/POPFD Pop EFLAGS from stack
STI Set interrupt flag
CLI Clear the interrupt flag

5.1.12 Segment Register Instructions

LDS Load far pointer using DS
LES Load far pointer using ES
LFS Load far pointer using FS
LGS Load far pointer using GS
LSS Load far pointer using SS

5.1.13 Miscellaneous Instructions

LEA Load effective address
NOP No operation
UD2 Undefined instruction
XLAT/XLATB Table lookup translation
CPUID Processor identification
MOVBE Move data after swapping data bytes

5.1.14 Random Number Generator Instruction
RDRAND Retrieves a random number generated from hardware.

5.1.15 BMI1, BMI2
ANDN Bitwise AND of first source with inverted 2nd source operands.
BEXTR Contiguous bitwise extract
BLSI Extract lowest set bit
BLSMK Set all lower bits below first set bit to 1
BLSR Reset lowest set bit
BZHI Zero high bits starting from specified bit position
LZCNT Count the number leading zero bits
MULX Unsigned multiply without affecting arithmetic flags
PDEP Parallel deposit of bits using a mask
PEXT Parallel extraction of bits using a mask
RORX Rotate right without affecting arithmetic flags
SARX Shift arithmetic right
SHLX Shift logic left
SHRX Shift logic right
TZCNT Count the number trailing zero bits

5.1.15.1 Detection of VEX-encoded GPR Instructions, LZCNT and TZCNT

CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]: if 1 indicates the processor supports the first group of advanced bit
manipulation extensions (ANDN, BEXTR, BLSI, BLSMK, BLSR, TZCNT);
CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]: if 1 indicates the processor supports the second group of advanced
bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX);
CPUID.EAX=80000001H:ECX.LZCNT[bit 5]: if 1 indicates the processor supports the LZCNT instruction.

5.2 X87 FPU INSTRUCTIONS

5.2.1 x87 FPU Data Transfer Instructions

FLD Load floating-point value
FST Store floating-point value
FSTP Store floating-point value and pop
FILD Load integer
FIST Store integer
FISTP1 Store integer and pop
FBLD Load BCD
FBSTP Store BCD and pop
FXCH Exchange registers
FCMOVE Floating-point conditional move if equal
FCMOVNE Floating-point conditional move if not equal
FCMOVB Floating-point conditional move if below
1. SSE3 provides an instruction FISTTP for integer conversion.
FCMOVBE Floating-point conditional move if below or equal
FCMOVNB Floating-point conditional move if not below
FCMOVNBE Floating-point conditional move if not below or equal
FCMOVU Floating-point conditional move if unordered
FCMOVNU Floating-point conditional move if not unordered

5.2.2 x87 FPU Basic Arithmetic Instructions

FADD Add floating-point
FADDP Add floating-point and pop
FIADD Add integer
FSUB Subtract floating-point
FSUBP Subtract floating-point and pop
FISUB Subtract integer
FSUBR Subtract floating-point reverse
FSUBRP Subtract floating-point reverse and pop
FISUBR Subtract integer reverse
FMUL Multiply floating-point
FMULP Multiply floating-point and pop
FIMUL Multiply integer
FDIV Divide floating-point
FDIVP Divide floating-point and pop
FIDIV Divide integer
FDIVR Divide floating-point reverse
FDIVRP Divide floating-point reverse and pop
FIDIVR Divide integer reverse
FPREM Partial remainder
FPREM1 IEEE Partial remainder
FABS Absolute value
FCHS Change sign
FRNDINT Round to integer
FSCALE Scale by power of two
FSQRT Square root
FXTRACT Extract exponent and significand

5.2.3 x87 FPU Comparison Instructions

FCOM Compare floating-point
FCOMP Compare floating-point and pop
FCOMPP Compare floating-point and pop twice
FUCOM Unordered compare floating-point
FUCOMP Unordered compare floating-point and pop
FUCOMPP Unordered compare floating-point and pop twice
FICOM Compare integer
FICOMP Compare integer and pop
FCOMI Compare floating-point and set EFLAGS
FUCOMI Unordered compare floating-point and set EFLAGS
FCOMIP Compare floating-point, set EFLAGS, and pop
FUCOMIP Unordered compare floating-point, set EFLAGS, and pop
FTST Test floating-point (compare with 0.0)
FXAM Examine floating-point

5.2.4 x87 FPU Transcendental Instructions

FSIN Sine
FCOS Cosine
FSINCOS Sine and cosine
FPTAN Partial tangent
FPATAN Partial arctangent
F2XM1 2x . 1
FYL2X y.log2x
FYL2XP1 y.log2(x+1)

5.2.5 x87 FPU Load Constants Instructions

FLD1 Load +1.0
FLDZ Load +0.0
FLDPI Load π
FLDL2E Load log2e
FLDLN2 Load loge2
FLDL2T Load log210
FLDLG2 Load log102

5.2.6 x87 FPU Control Instructions

FINCSTP Increment FPU register stack pointer
FDECSTP Decrement FPU register stack pointer
FFREE Free floating-point register
FINIT Initialize FPU after checking error conditions
FNINIT Initialize FPU without checking error conditions
FCLEX Clear floating-point exception flags after checking for error
conditions
FNCLEX Clear floating-point exception flags without checking for error
conditions
FSTCW Store FPU control word after checking error conditions
FNSTCW Store FPU control word without checking error conditions
FLDCW Load FPU control word
FSTENV Store FPU environment after checking error conditions
FNSTENV Store FPU environment without checking error conditions
FLDENV Load FPU environment
FSAVE Save FPU state after checking error conditions
FNSAVE Save FPU state without checking error conditions
FRSTOR Restore FPU state
FSTSW Store FPU status word after checking error conditions
FNSTSW Store FPU status word without checking error conditions
WAIT/FWAIT Wait for FPU
FNOP FPU no operation

5.3 X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS

FXSAVE Save x87 FPU and SIMD state
FXRSTOR Restore x87 FPU and SIMD state
Initially, these instructions operated only on the x87 FPU (and MMX) registers to perform a fast save and restore,
respectively, of the x87 FPU and MMX state. With the introduction of SSE extensions in the Pentium III processor
family, these instructions were expanded to also save and restore the state of the XMM and MXCSR registers. Intel
64 architecture also supports these instructions.
See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for more detail.

5.4 MMX™ INSTRUCTIONS

5.4.1 MMX Data Transfer Instructions

MMX registers and memory.
MOVD Move doubleword
MOVQ Move quadword

5.4.2 MMX Conversion Instructions

PACKSSWB Pack words into bytes with signed saturation
PACKSSDW Pack doublewords into words with signed saturation
PACKUSWB Pack words into bytes with unsigned saturation.
PUNPCKHBW Unpack high-order bytes
PUNPCKHWD Unpack high-order words
PUNPCKHDQ Unpack high-order doublewords
PUNPCKLBW Unpack low-order bytes
PUNPCKLWD Unpack low-order words
PUNPCKLDQ Unpack low-order doublewords

5.4.3 MMX Packed Arithmetic Instructions

PADDB Add packed byte integers
PADDW Add packed word integers
PADDD Add packed doubleword integers
PADDSB Add packed signed byte integers with signed saturation
PADDSW Add packed signed word integers with signed saturation
PADDUSB Add packed unsigned byte integers with unsigned saturation
PADDUSW Add packed unsigned word integers with unsigned saturation
PSUBB Subtract packed byte integers
PSUBW Subtract packed word integers
PSUBD Subtract packed doubleword integers
PSUBSB Subtract packed signed byte integers with signed saturation
PSUBSW Subtract packed signed word integers with signed saturation
PSUBUSB Subtract packed unsigned byte integers with unsigned saturation
PSUBUSW Subtract packed unsigned word integers with unsigned
saturation
PMULHW Multiply packed signed word integers and store high result
PMULLW Multiply packed signed word integers and store low result
PMADDWD Multiply and add packed word integers

5.4.4 MMX Comparison Instructions

PCMPEQB Compare packed bytes for equal
PCMPEQW Compare packed words for equal
PCMPEQD Compare packed doublewords for equal
PCMPGTB Compare packed signed byte integers for greater than
PCMPGTW Compare packed signed word integers for greater than
PCMPGTD Compare packed signed doubleword integers for greater than

5.4.5 MMX Logical Instructions

PAND Bitwise logical AND
PANDN Bitwise logical AND NOT
POR Bitwise logical OR
PXOR Bitwise logical exclusive OR

5.4.6 MMX Shift and Rotate Instructions

PSLLW Shift packed words left logical
PSLLD Shift packed doublewords left logical
PSLLQ Shift packed quadword left logical
PSRLW Shift packed words right logical
PSRLD Shift packed doublewords right logical
PSRLQ Shift packed quadword right logical
PSRAW Shift packed words right arithmetic
PSRAD Shift packed doublewords right arithmetic

5.4.7 MMX State Management Instructions

EMMS Empty MMX state

5.5 SSE INSTRUCTIONS

5.5.1.1 SSE Data Transfer Instructions

MOVAPS Move four aligned packed single-precision floating-point values between XMM registers or
between and XMM register and memory
MOVUPS Move four unaligned packed single-precision floating-point values between XMM registers or
between and XMM register and memory
MOVHPS Move two packed single-precision floating-point values to an from the high quadword of an
XMM register and memory
MOVHLPS Move two packed single-precision floating-point values from the high quadword of an XMM
register to the low quadword of another XMM register
MOVLPS Move two packed single-precision floating-point values to an from the low quadword of an
XMM register and memory
MOVLHPS Move two packed single-precision floating-point values from the low quadword of an XMM
register to the high quadword of another XMM register
MOVMSKPS Extract sign mask from four packed single-precision floating-point values
MOVSS Move scalar single-precision floating-point value between XMM registers or between an XMM
register and memory

5.5.1.2 SSE Packed Arithmetic Instructions

ADDPS Add packed single-precision floating-point values
ADDSS Add scalar single-precision floating-point values
SUBPS Subtract packed single-precision floating-point values
SUBSS Subtract scalar single-precision floating-point values
MULPS Multiply packed single-precision floating-point values
MULSS Multiply scalar single-precision floating-point values
DIVPS Divide packed single-precision floating-point values
DIVSS Divide scalar single-precision floating-point values
RCPPS Compute reciprocals of packed single-precision floating-point values
RCPSS Compute reciprocal of scalar single-precision floating-point values
SQRTPS Compute square roots of packed single-precision floating-point values
SQRTSS Compute square root of scalar single-precision floating-point values
RSQRTPS Compute reciprocals of square roots of packed single-precision floating-point values
RSQRTSS Compute reciprocal of square root of scalar single-precision floating-point values
MAXPS Return maximum packed single-precision floating-point values
MAXSS Return maximum scalar single-precision floating-point values
MINPS Return minimum packed single-precision floating-point values
MINSS Return minimum scalar single-precision floating-point values

5.5.1.3 SSE Comparison Instructions

CMPPS Compare packed single-precision floating-point values
CMPSS Compare scalar single-precision floating-point values
COMISS Perform ordered comparison of scalar single-precision floating-point values and set flags in
EFLAGS register
UCOMISS Perform unordered comparison of scalar single-precision floating-point values and set flags in
EFLAGS register

5.5.1.4 SSE Logical Instructions

ANDPS Perform bitwise logical AND of packed single-precision floating-point values
ANDNPS Perform bitwise logical AND NOT of packed single-precision floating-point values
ORPS Perform bitwise logical OR of packed single-precision floating-point values
XORPS Perform bitwise logical XOR of packed single-precision floating-point values

5.5.1.5 SSE Shuffle and Unpack Instructions

SHUFPS Shuffles values in packed single-precision floating-point
operands
UNPCKHPS Unpacks and interleaves the two high-order values from two single-precision floating-point
operands
UNPCKLPS Unpacks and interleaves the two low-order values from two single-precision floating-point
operands

5.5.1.6 SSE Conversion Instructions

CVTPI2PS Convert packed doubleword integers to packed single-precision floating-point values
CVTSI2SS Convert doubleword integer to scalar single-precision floating-point value
CVTPS2PI Convert packed single-precision floating-point values to packed doubleword integers
CVTTPS2PI Convert with truncation packed single-precision floating-point values to packed doubleword
integers
CVTSS2SI Convert a scalar single-precision floating-point value to a doubleword integer
CVTTSS2SI Convert with truncation a scalar single-precision floating-point value to a scalar doubleword
integer

5.5.2 SSE MXCSR State Management Instructions

MXCSR state management instructions allow saving and restoring the state of the MXCSR control and status
register.
LDMXCSR Load MXCSR register
STMXCSR Save MXCSR register state

5.5.3 SSE 64-Bit SIMD Integer Instructions

PAVGB Compute average of packed unsigned byte integers
PAVGW Compute average of packed unsigned word integers
PEXTRW Extract word
PINSRW Insert word
PMAXUB Maximum of packed unsigned byte integers
PMAXSW Maximum of packed signed word integers
PMINUB Minimum of packed unsigned byte integers
PMINSW Minimum of packed signed word integers
PMOVMSKB Move byte mask
PMULHUW Multiply packed unsigned integers and store high result
PSADBW Compute sum of absolute differences
PSHUFW Shuffle packed integer word in MMX register

5.5.4 SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions

MASKMOVQ Non-temporal store of selected bytes from an MMX register into memory
MOVNTQ Non-temporal store of quadword from an MMX register into memory
MOVNTPS Non-temporal store of four packed single-precision floating-point values from an XMM register
into memory
PREFETCHh Load 32 or more of bytes from memory to a selected level of the processor’s cache hierarchy
SFENCE Serializes store operations

5.6 SSE2 INSTRUCTIONS

5.6.1.1 SSE2 Data Movement Instructions

MOVAPD Move two aligned packed double-precision floating-point values between XMM registers or
between and XMM register and memory
MOVUPD Move two unaligned packed double-precision floating-point values between XMM registers or
between and XMM register and memory
MOVHPD Move high packed double-precision floating-point value to an from the high quadword of an
XMM register and memory
MOVLPD Move low packed single-precision floating-point value to an from the low quadword of an XMM
register and memory
MOVMSKPD Extract sign mask from two packed double-precision floating-point values
MOVSD Move scalar double-precision floating-point value between XMM registers or between an XMM
register and memory

5.6.1.2 SSE2 Packed Arithmetic Instructions

ADDPD Add packed double-precision floating-point values
ADDSD Add scalar double precision floating-point values
SUBPD Subtract scalar double-precision floating-point values
SUBSD Subtract scalar double-precision floating-point values
MULPD Multiply packed double-precision floating-point values
MULSD Multiply scalar double-precision floating-point values
DIVPD Divide packed double-precision floating-point values
DIVSD Divide scalar double-precision floating-point values
SQRTPD Compute packed square roots of packed double-precision floating-point values
SQRTSD Compute scalar square root of scalar double-precision floating-point values
MAXPD Return maximum packed double-precision floating-point values
MAXSD Return maximum scalar double-precision floating-point values
MINPD Return minimum packed double-precision floating-point values
MINSD Return minimum scalar double-precision floating-point values

5.6.1.3 SSE2 Logical Instructions

ANDPD Perform bitwise logical AND of packed double-precision floating-point values
ANDNPD Perform bitwise logical AND NOT of packed double-precision floating-point values
ORPD Perform bitwise logical OR of packed double-precision floating-point values
XORPD Perform bitwise logical XOR of packed double-precision floating-point values

5.6.1.4 SSE2 Compare Instructions

CMPPD Compare packed double-precision floating-point values
CMPSD Compare scalar double-precision floating-point values
COMISD Perform ordered comparison of scalar double-precision floating-point values and set flags in
EFLAGS register
UCOMISD Perform unordered comparison of scalar double-precision floating-point values and set flags in
EFLAGS register.

5.6.1.5 SSE2 Shuffle and Unpack Instructions

SHUFPD Shuffles values in packed double-precision floating-point
operands
UNPCKHPD Unpacks and interleaves the high values from two packed double-precision floating-point
operands
UNPCKLPD Unpacks and interleaves the low values from two packed double-precision floating-point operands

5.6.1.6 SSE2 Conversion Instructions

CVTPD2PI Convert packed double-precision floating-point values to packed doubleword integers.
CVTTPD2PI Convert with truncation packed double-precision floating-point values to packed doubleword
integers
CVTPI2PD Convert packed doubleword integers to packed double-precision floating-point values
CVTPD2DQ Convert packed double-precision floating-point values to packed doubleword integers
CVTTPD2DQ Convert with truncation packed double-precision floating-point values to packed doubleword
integers
CVTDQ2PD Convert packed doubleword integers to packed double-precision floating-point values
CVTPS2PD Convert packed single-precision floating-point values to packed double-precision floatingpoint
values
CVTPD2PS Convert packed double-precision floating-point values to packed single-precision floatingpoint
values
CVTSS2SD Convert scalar single-precision floating-point values to scalar double-precision floating-point
values
CVTSD2SS Convert scalar double-precision floating-point values to scalar single-precision floating-point
values
CVTSD2SI Convert scalar double-precision floating-point values to a doubleword integer
CVTTSD2SI Convert with truncation scalar double-precision floating-point values to scalar doubleword
integers
CVTSI2SD Convert doubleword integer to scalar double-precision floating-point value

5.6.2 SSE2 Packed Single-Precision Floating-Point Instructions

CVTDQ2PS Convert packed doubleword integers to packed single-precision floating-point values
CVTPS2DQ Convert packed single-precision floating-point values to packed doubleword integers
CVTTPS2DQ Convert with truncation packed single-precision floating-point values to packed doubleword
integers

5.6.3 SSE2 128-Bit SIMD Integer Instructions

MOVDQA Move aligned double quadword.
MOVDQU Move unaligned double quadword
MOVQ2DQ Move quadword integer from MMX to XMM registers
MOVDQ2Q Move quadword integer from XMM to MMX registers
PMULUDQ Multiply packed unsigned doubleword integers
PADDQ Add packed quadword integers
PSUBQ Subtract packed quadword integers
PSHUFLW Shuffle packed low words
PSHUFHW Shuffle packed high words
PSHUFD Shuffle packed doublewords
PSLLDQ Shift double quadword left logical
PSRLDQ Shift double quadword right logical
PUNPCKHQDQ Unpack high quadwords
PUNPCKLQDQ Unpack low quadwords

5.6.4 SSE2 Cacheability Control and Ordering Instructions

CLFLUSH Flushes and invalidates a memory operand and its associated cache line from all levels of the
processor’s cache hierarchy
LFENCE Serializes load operations
MFENCE Serializes load and store operations
PAUSE Improves the performance of “spin-wait loops”
MASKMOVDQU Non-temporal store of selected bytes from an XMM register into memory
MOVNTPD Non-temporal store of two packed double-precision floating-point values from an XMM
register into memory
MOVNTDQ Non-temporal store of double quadword from an XMM register into memory
MOVNTI Non-temporal store of a doubleword from a general-purpose register into memory

5.7 SSE3 INSTRUCTIONS

5.7.1 SSE3 x87-FP Integer Conversion Instruction

FISTTP Behaves like the FISTP instruction but uses truncation, irrespective of the rounding mode
specified in the floating-point control word (FCW)

5.7.2 SSE3 Specialized 128-bit Unaligned Data Load Instruction
LDDQU Special 128-bit unaligned load designed to avoid cache line splits

5.7.3 SSE3 SIMD Floating-Point Packed ADD/SUB Instructions

ADDSUBPS Performs single-precision addition on the second and fourth pairs of 32-bit data elements
within the operands; single-precision subtraction on the first and third pairs
ADDSUBPD Performs double-precision addition on the second pair of quadwords, and double-precision
subtraction on the first pair

5.7.4 SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions

HADDPS Performs a single-precision addition on contiguous data elements. The first data element of
the result is obtained by adding the first and second elements of the first operand; the second
element by adding the third and fourth elements of the first operand; the third by adding the
first and second elements of the second operand; and the fourth by adding the third and fourth
elements of the second operand.
HSUBPS Performs a single-precision subtraction on contiguous data elements. The first data element of
the result is obtained by subtracting the second element of the first operand from the first
element of the first operand; the second element by subtracting the fourth element of the first
operand from the third element of the first operand; the third by subtracting the second
element of the second operand from the first element of the second operand; and the fourth
by subtracting the fourth element of the second operand from the third element of the second
operand.
HADDPD Performs a double-precision addition on contiguous data elements. The first data element of
the result is obtained by adding the first and second elements of the first operand; the second
element by adding the first and second elements of the second operand.
HSUBPD Performs a double-precision subtraction on contiguous data elements. The first data element
of the result is obtained by subtracting the second element of the first operand from the first
element of the first operand; the second element by subtracting the second element of the
second operand from the first element of the second operand.

5.7.5 SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions

MOVSHDUP Loads/moves 128 bits; duplicating the second and fourth 32-bit data elements
MOVSLDUP Loads/moves 128 bits; duplicating the first and third 32-bit data elements
MOVDDUP Loads/moves 64 bits (bits[63:0] if the source is a register) and returns the same 64 bits in
both the lower and upper halves of the 128-bit result register; duplicates the 64 bits from the
source

5.7.6 SSE3 Agent Synchronization Instructions
MONITOR Sets up an address range used to monitor write-back stores
MWAIT Enables a logical processor to enter into an optimized state while waiting for a write-back store
to the address range set up by the MONITOR instruction

5.8 SUPPLEMENTAL STREAMING SIMD EXTENSIONS 3 (SSSE3) INSTRUCTIONS

5.8.1 Horizontal Addition/Subtraction

PHADDW Adds two adjacent, signed 16-bit integers horizontally from the source and destination operands
and packs the signed 16-bit results to the destination operand.
PHADDSW Adds two adjacent, signed 16-bit integers horizontally from the source and destination operands
and packs the signed, saturated 16-bit results to the destination operand.
PHADDD Adds two adjacent, signed 32-bit integers horizontally from the source and destination operands
and packs the signed 32-bit results to the destination operand.
PHSUBW Performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting
the most significant word from the least significant word of each pair in the source and destination
operands. The signed 16-bit results are packed and written to the destination operand.
PHSUBSW Performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting
the most significant word from the least significant word of each pair in the source and destination
operands. The signed, saturated 16-bit results are packed and written to the destination
operand.
PHSUBD Performs horizontal subtraction on each adjacent pair of 32-bit signed integers by subtracting
the most significant doubleword from the least significant double word of each pair in the
source and destination operands. The signed 32-bit results are packed and written to the
destination operand.

5.8.2 Packed Absolute Values

PABSB Computes the absolute value of each signed byte data element.
PABSW Computes the absolute value of each signed 16-bit data element.
PABSD Computes the absolute value of each signed 32-bit data element.

5.8.3 Multiply and Add Packed Signed and Unsigned Bytes
PMADDUBSW Multiplies each unsigned byte value with the corresponding signed byte value to produce an
intermediate, 16-bit signed integer. Each adjacent pair of 16-bit signed values are added horizontally.
The signed, saturated 16-bit results are packed to the destination operand.

5.8.4 Packed Multiply High with Round and Scale

PMULHRSW Multiplies vertically each signed 16-bit integer from the destination operand with the corresponding
signed 16-bit integer of the source operand, producing intermediate, signed 32-bit
integers. Each intermediate 32-bit integer is truncated to the 18 most significant bits.
Rounding is always performed by adding 1 to the least significant bit of the 18-bit intermediate
result. The final result is obtained by selecting the 16 bits immediately to the right of the most
significant bit of each 18-bit intermediate result and packed to the destination operand.

5.8.5 Packed Shuffle Bytes

PSHUFB Permutes each byte in place, according to a shuffle control mask. The least significant three or
four bits of each shuffle control byte of the control mask form the shuffle index. The shuffle
mask is unaffected. If the most significant bit (bit 7) of a shuffle control byte is set, the
constant zero is written in the result byte.

5.8.6 Packed Sign

PSIGNB/W/D Negates each signed integer element of the destination operand if the sign of the corresponding
data element in the source operand is less than zero.

5.8.7 Packed Align Right

PALIGNR Source operand is appended after the destination operand forming an intermediate value of
twice the width of an operand. The result is extracted from the intermediate value into the
destination operand by selecting the 128 bit or 64 bit value that are right-aligned to the byte
offset specified by the immediate value.

5.10 SSE4.1 INSTRUCTIONS

5.10.1 Dword Multiply Instructions

PMULLD Returns four lower 32-bits of the 64-bit results of signed 32-bit integer multiplies.
PMULDQ Returns two 64-bit signed result of signed 32-bit integer multiplies.

5.10.2 Floating-Point Dot Product Instructions

DPPD Perform double-precision dot product for up to 2 elements and broadcast.
DPPS Perform single-precision dot products for up to 4 elements and broadcast

5.10.3 Streaming Load Hint Instruction

MOVNTDQA Provides a non-temporal hint that can cause adjacent 16-byte items within an aligned 64-byte
region (a streaming line) to be fetched and held in a small set of temporary buffers
(“streaming load buffers”). Subsequent streaming loads to other aligned 16-byte items in the
same streaming line may be supplied from the streaming load buffer and can improve
throughput.

5.10.4 Packed Blending Instructions

BLENDPD Conditionally copies specified double-precision floating-point data elements in the source
operand to the corresponding data elements in the destination, using an immediate byte
control.
BLENDPS Conditionally copies specified single-precision floating-point data elements in the source
operand to the corresponding data elements in the destination, using an immediate byte
control.
BLENDVPD Conditionally copies specified double-precision floating-point data elements in the source
operand to the corresponding data elements in the destination, using an implied mask.
BLENDVPS Conditionally copies specified single-precision floating-point data elements in the source
operand to the corresponding data elements in the destination, using an implied mask.
PBLENDVB Conditionally copies specified byte elements in the source operand to the corresponding
elements in the destination, using an implied mask.
PBLENDW Conditionally copies specified word elements in the source operand to the corresponding
elements in the destination, using an immediate byte control.

5.10.5 Packed Integer MIN/MAX Instructions

PMINUW Compare packed unsigned word integers.
PMINUD Compare packed unsigned dword integers.
PMINSB Compare packed signed byte integers.
PMINSD Compare packed signed dword integers.
PMAXUW Compare packed unsigned word integers.
PMAXUD Compare packed unsigned dword integers.
PMAXSB Compare packed signed byte integers.
PMAXSD Compare packed signed dword integers.

5.10.6 Floating-Point Round Instructions with Selectable Rounding Mode

ROUNDPS Round packed single precision floating-point values into integer values and return rounded
floating-point values.
ROUNDPD Round packed double precision floating-point values into integer values and return rounded
floating-point values.
ROUNDSS Round the low packed single precision floating-point value into an integer value and return a
rounded floating-point value.
ROUNDSD Round the low packed double precision floating-point value into an integer value and return a
rounded floating-point value.

5.10.7 Insertion and Extractions from XMM Registers

EXTRACTPS Extracts a single-precision floating-point value from a specified offset in an XMM register and
stores the result to memory or a general-purpose register
INSERTPS Inserts a single-precision floating-point value from either a 32-bit memory location or selected
from a specified offset in an XMM register to a specified offset in the destination XMM register.
In addition, INSERTPS allows zeroing out selected data elements in the destination, using a
mask.
PINSRB Insert a byte value from a register or memory into an XMM register
PINSRD Insert a dword value from 32-bit register or memory into an XMM register
PINSRQ Insert a qword value from 64-bit register or memory into an XMM register
PEXTRB Extract a byte from an XMM register and insert the value into a general-purpose register or
memory
PEXTRW Extract a word from an XMM register and insert the value into a general-purpose register or
memory
PEXTRD Extract a dword from an XMM register and insert the value into a general-purpose register or
memory
PEXTRQ Extract a qword from an XMM register and insert the value into a general-purpose register or
memory

5.10.8 Packed Integer Format Conversions

PMOVSXBW Sign extend the lower 8-bit integer of each packed word element into packed signed word
integers.
PMOVZXBW Zero extend the lower 8-bit integer of each packed word element into packed signed word
integers.
PMOVSXBD Sign extend the lower 8-bit integer of each packed dword element into packed signed dword
integers.
PMOVZXBD Zero extend the lower 8-bit integer of each packed dword element into packed signed dword
integers.
PMOVSXWD Sign extend the lower 16-bit integer of each packed dword element into packed signed dword
integers.
PMOVZXWD Zero extend the lower 16-bit integer of each packed dword element into packed signed dword
integers..
PMOVSXBQ Sign extend the lower 8-bit integer of each packed qword element into packed signed qword
integers.
PMOVZXBQ Zero extend the lower 8-bit integer of each packed qword element into packed signed qword
integers.
PMOVSXWQ Sign extend the lower 16-bit integer of each packed qword element into packed signed qword
integers.
PMOVZXWQ Zero extend the lower 16-bit integer of each packed qword element into packed signed qword
integers.
PMOVSXDQ Sign extend the lower 32-bit integer of each packed qword element into packed signed qword
integers.
PMOVZXDQ Zero extend the lower 32-bit integer of each packed qword element into packed signed qword
integers.

5.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks

MPSADBW Performs eight 4-byte wide Sum of Absolute Differences operations to produce eight word
integers.

5.10.10 Horizontal Search

PHMINPOSUW Finds the value and location of the minimum unsigned word from one of 8 horizontally packed
unsigned words. The resulting value and location (offset within the source) are packed into
the low dword of the destination XMM register.

5.11.1 String and Text Processing Instructions

PCMPESTRI Packed compare explicit-length strings, return index in ECX/RCX
PCMPESTRM Packed compare explicit-length strings, return mask in XMM0
PCMPISTRI Packed compare implicit-length strings, return index in ECX/RCX
PCMPISTRM Packed compare implicit-length strings, return mask in XMM0

5.11.2 Packed Comparison SIMD integer Instruction

PCMPGTQ Performs logical compare of greater-than on packed integer quadwords.

5.18 SYSTEM INSTRUCTIONS

LGDT Load global descriptor table (GDT) register
SGDT Store global descriptor table (GDT) register
LLDT Load local descriptor table (LDT) register
SLDT Store local descriptor table (LDT) register
LTR Load task register
STR Store task register
LIDT Load interrupt descriptor table (IDT) register
SIDT Store interrupt descriptor table (IDT) register
MOV Load and store control registers
LMSW Load machine status word
SMSW Store machine status word
CLTS Clear the task-switched flag
ARPL Adjust requested privilege level
LAR Load access rights
LSL Load segment limit
VERR Verify segment for reading
VERW Verify segment for writing
MOV Load and store debug registers
INVD Invalidate cache, no writeback
WBINVD Invalidate cache, with writeback
INVLPG Invalidate TLB Entry
INVPCID Invalidate Process-Context Identifier
LOCK (prefix) Lock Bus
HLT Halt processor
RSM Return from system management mode (SMM)
RDMSR Read model-specific register
WRMSR Write model-specific register
RDPMC Read performance monitoring counters
RDTSC Read time stamp counter
RDTSCP Read time stamp counter and processor ID
SYSENTER Fast System Call, transfers to a flat protected mode kernel at CPL = 0
SYSEXIT Fast System Call, transfers to a flat protected mode kernel at CPL = 3
XSAVE Save processor extended states to memory
XSAVEOPT Save processor extended states to memory, optimized
XRSTOR Restore processor extended states from memory
XGETBV Reads the state of an extended control register
XSETBV Writes the state of an extended control register
RDFSBASE Reads from FS base address at any privilege level
RDGSBASE Reads from GS base address at any privilege level
WRFSBASE Writes to FS base address at any privilege level
WRGSBASE Writes to GS base address at any privilege level

5.19 64-BIT MODE INSTRUCTIONS

CDQE Convert doubleword to quadword
CMPSQ Compare string operands
CMPXCHG16B Compare RDX:RAX with m128
LODSQ Load qword at address (R)SI into RAX
MOVSQ Move qword from address (R)SI to (R)DI
MOVZX (64-bits) Move doubleword to quadword, zero-extension
STOSQ Store RAX at address RDI
SWAPGS Exchanges current GS base register value with value in MSR address C0000102H
SYSCALL Fast call to privilege level 0 system procedures
SYSRET Return from fast system call